We are certified as a Research Institute from the Korea Industrial Technology Association (KOITA).

We are certified as a Vencture Business from the Ministry of MSEs and Startups of Korea.

A patent of "FRAME SYNCHRONIZATION SIGNAL INSERSION DEVICE AND METHOD OF TOMOGRAPHY SYSTEM" is granted.

Future Design Systems announced facemask detection application of deep learning acceration for edge-computing using ZCU102, in which deep learning object detection inference engine is running in the FPGA.

Future Design Systems announced facemask detection application of deep learning acceration for server using DeepAccel, in which deep learning object detection inference engine is running in the FPGA through PCI-Express.

New product for Artificial intelligence (AI) / Deep Learning (DL) development package

Future Design Systems announced DLR (Deep Learning Routines) package, which is a collection of high-level synthesizable C routines for deep learning inference network.

Future Design Systems announced an example of running facemask detection on FPGA/DeepAccel-KU/DeepAccel-DualVU9P.

Future Design Systems announced an new product for multi-giga sampline of ADC/DAC.

Future Design Systems announced an example of running YOLO V2 on FPGA/DeepAccel-DualVU9P, in which PC (Linux) controls the FPGA through PCI-Express.

Future Design Systems announced a novel approach of YOLO V2 on FPGA, in which Raspberry Pi controls the FPGA through USB/CON-FMC.

Future Design Systems adds new product line for Deep-Learning accelerator; DeepAccel-DualVU9P.

Year 2020 of Future Design Systems will be a turning point.

Future Design Systems announced a novel approach to run Deep-Learning application on FPGA, in which Raspberry Pi controls the FPGA through USB/CON-FMC.

Future Design Systems successfully completed "Development of HPC System for Accelerating Large-Scale Deep Learning" project, which is funded by the Ministry of Science and ICT(MSIT, Korea).

Future Design Systems is taking in part of CUOP program, in which an intern is joined with Future Design Systems.

Future Design Systems successfully completed dual-FPGA (Xilinx UltraScale+) AI/ML accelerator under the contract with SK Telecom.

Future Design Systems is taking in part of Internship program with KOSAF.

We are now a member of Handong Global University IACF. Handong Global University IACF (Industry-Academic Cooperation Foundation).

Future Design Systems is taking in part of ICT Internship program.

Future Design Systems prepares GitHub repository for CON-FMC SW ( Linux and Windows) and examples.

Future Design Systems runs sessions at the workshop hosted by The Korean Institute of Communications and Information Science. The workshop is held at Soongsil University on June 7, 2019. Program

Python interface package for CON-FMC is ready. This package enables user to run CON-FMC API and functions from Python.

Future Design Systems contracts with Sejong University to develop D-OCT system.

Year 2019 of Future Design Systems will be a remarkable.

Future Design Systems developed neural signal interface system. This system consisting of NeuralFMC, FPGA board, and CON-FMC gets neural signals through FPGA and USB3.0. Each NeuralFMC board support up to 128 ADC channels.

A patent of "APPARATUS AND METHOD FOR COMPUTING A SPARSE MATRIX" is granted. The patent is related with deep-learning computation.

Future Design Systems is taking in part of CUOP program, in which two interns are joined with Future Design Systems.

Future Design Systems developed IEC 62439-3 HSR (High-availability Seamless Redundancy), which is one of fault tolerant network standards. The HSR products are tested and got certificates by TTA (Telecommunications Technology Association) on Oct. 30, 2018. Future Design Systems has plan to deploy the products in the application areas requires fault tolerance and real-time.

FMC-GbE-RJ45 is ready as a new product. FMC-GbE-RJ45 is an FMC (FPGA Mezzanine Card) board compliant with the VITA 57.1 standard supporting three Gigabit Ethernet ports.

CON-FMC on MagPi Magazin Issue 73 page 95.

Memorandum of Understanding between Future Design Systems and SK Telecom is made on development of On-Devie AI System.

Four-day lecture on OpenCL (Open Computing Language) at FastCampus on April to September. This lecture focuses on OpenCL for Xilinx FPGA and uses AWS EC2 F1 instance.

CON-FMC now supporting Samsung ARTIK board.

Future Design Systems contracts with SK Telecom to develop FPGA-based AI accelerator.

Two patents are pending, which are related on computation acceleration of artificial intelligence (deep learning) applications.

Future Design Systems receives a grant from Daejeon Technopark for "Develpment of USB3.0 platform processing neural signals" project.

Two-day public lecture on OpenCL (Open Computing Language) at IDEC KAIST (idec.kaist.ac.kr) on April 3-4, 2018. It includes introduction of OpenCL and hands-on practice using Intel CPU, Xilinx SDAccel for FPGA. The OpenCL examples include vector addition, matrix multiplicaion, convolution, and so on. Each example covers specific topics of OpenCL such as online/offline compilation, optimization using local memory, vector data types, image data type, sychronization, and more.

We have been approved as a member of Xilinx Alliance Program for year 2018. The Xilinx Alliance Program is a worldwide ecosystem of qualified companies collaborating with Xilinx to further the development of All Programmable technologies.

Two-day public lecture on Deep Learning at IDEC KAIST on Jan. 10-11, 2018. It includes introduction of AI/ML/DL and hands-on practice using TensorFlow, Darknet/YOLO, Tiny-DNN.

Future Design Systems takes part in "Development of HPC System for Accelerating Large-Scale Deep Learning" project, which is funded by the Ministry of Science and ICT(MSIT, Korea).

Year 2018 of Future Design Systems will be a next step to the future.

We are now a member of CUOP (Company University Cooeration) Program.

We are now a certified company of Symantec Inc. from COROSSCERT; Korea Electronic Certification Authority Inc.

We are now a member of Xilinx Alliance Program. The Xilinx Alliance Program is a worldwide ecosystem of qualified companies collaborating with Xilinx to further the development of All Programmable technologies.

CON-FMC is ready as a new product. CON-FMC is a USB 3.0 FMC (FPGA Mezzanine Card) board compliant with the VITA 57.1 standard.

We are now a member of Hanbat Natioanl University IUCF. Hanbat National University IUCF (Industry-University Cooperation Foundation).

We are certified as a Vencture Business from Small and Medium Business Corporation.

We are now a member of TBC (Technology Business Incubation Center) of OUIC KAIST. KAIST OUIC (Office of University-Industry Cooperation).